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feat(SV P0): SCL-preserved IEC Ed2.1 4I4V smpRate/smpMod wire profiles - #285

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masarray wants to merge 5 commits into
fix/ptp-source-fast-auto-lock-20261022from
feat/sv-ed21-rate-metadata-20261022
Closed

masarray wants to merge 5 commits into
fix/ptp-source-fast-auto-lock-20261022from
feat/sv-ed21-rate-metadata-20261022

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Source and safety

  • Stacked on latest PR fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 SOURCE_FAST full chain: exact baseline 1846fd003c97bbf58e482efe11bd2a4a69a0eac7; not main.
  • 4I4V binary publisher preserves SCL sampling basis: SmpPerPeriod -> smpMod=0 and e.g. smpRate=80 for 4kHz@50Hz / 4.8kHz@60Hz; SmpPerSec -> smpMod=1 and rate 4000 or 4800. Validate actual frame-rate ratio 50/60 before admitting binary SCL mode.
  • Legacy 9-2LE SCL optional omission remains valid and default include_sample_rate=false remains unchanged; ASCII PROFILE SV uses established samples/second mode and resets any stale SCL wire mode.
  • STOP/START, PTP FSM and shared EMAC/GPTimer cadence not modified. Binary layout 4I4V descriptor and transactional BINCOMMIT remain fail-closed.
  • Studio inspector displays exact decoded SCL-selected wire smpRate/smpMod, explicitly shows absent optional fields.
  • Portable regression added for binary profile 50/60Hz, per-period wire BER and contradictory declared cadence rejection.

Gates

  • Exact-SHA compiler/ESP32 IDF, C++ native tests and Windows native preview required before calling CI DONE. PCAP physical, actual SIPROTEC acceptance and failover remain pending. Keep DRAFT and do not merge main.

@masarray
masarray marked this pull request as ready for review October 22, 2026 07:39
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Codex Review Summary

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Review Status Commit Review trigger
📝 Code Review ✅ Completed 2026-10-22T08:02:30.886315Z 88575b8 Draft marked ready
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💡 Codex Review

Here are some automated review suggestions for this pull request.

Reviewed commit: 17a4fec776

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Comment on lines +527 to +528
? QVariant::fromValue(p.timing.sampling_basis == SvSampleMode::samples_per_period
? 0 : p.timing.sampling_basis == SvSampleMode::samples_per_second ? 1 : -1)

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P2 Badge Map SecPerSample to smpMod 2

When an opened SCL uses the supported SecPerSample/SecPerSmp sampling basis with SmvOpts@sampleRate=true, the compiler produces SvSampleMode::seconds_per_sample, but this ternary falls through to -1. The new inspector therefore reports smpMod -1 instead of the corresponding wire value 2; handle the third known mode explicitly and reserve the fallback for genuinely unknown values.

AGENTS.md reference: AGENTS.md:L300-L301

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@masarray
masarray marked this pull request as draft October 22, 2026 07:57
@masarray
masarray marked this pull request as ready for review October 22, 2026 07:57

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💡 Codex Review

Here are some automated review suggestions for this pull request.

Reviewed commit: 88575b874f

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  • Mark a draft as ready
  • Comment "@codex review".

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Comment on lines +393 to +394
if ($sha -cnotmatch '^[0-9a-f]{40}
uses: actions/upload-artifact@v4

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P1 Badge Repair the malformed preview workflow

In the windows-preview job, the run: | block ends prematurely at the dedented uses: line, leaving the SHA regex unterminated and line 403 as an invalid top-level YAML key. A YAML parse reports could not find expected ':', so GitHub cannot load this workflow and none of its firmware or Windows preview jobs can run; keep the complete SHA check inside the PowerShell block and remove the misplaced duplicate artifact step.

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Disposition (2026-10-23): SUPERSEDED BY canonical Draft PR #286, NOT MERGED INTO main.

  • Source head 88575b874f35827afa54c86f294e11a798f6b8ae is an exact ancestor of integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 head 8c58e73809e8460b1a7e2e84187a14eae594a7d0: GitHub compare is ahead, 0 behind. The SCL-preserved Ed2.1 4I4V smpRate/smpMod source and regression changes are preserved in canonical integration history; no separate cherry-pick or source-branch deletion.
  • Following user physical feedback on 2026-10-23, local PTP/SV synchronization is reported to complete in ≤10 seconds. Earlier independent capture demonstrated smpSynch 0→2 at approximately 4.25 seconds on a different earlier firmware. This does not by itself prove receiver PTP LOCKED, full relay interop, or long soak.
  • Still open in integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 acceptance: SIPROTEC physical 4I4V acceptance, 4800 fps/60 Hz physical matrix where required, and any exact-head full CI not executed for Draft. These are NOT being declared completed by closing this redundant source PR.
  • Closure is housekeeping of an ancestry-contained, superseded branch. PR integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 remains Draft/unmerged; leave this branch intact for provenance.

@masarray masarray closed this Oct 23, 2026
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